Improving Processor Efficiency by Statically Pipelining Instructions

A new generation of mobile applications requires reduced energy consumption without sacrificing execution performance. A common approach for improving performance of processors is instruction pipelining. The way pipelining is traditionally implemented, however, is wasteful with regards to energy. This dissertation describes the design and implementation of an innovative \textit{statically pipelined} processor supported by an optimizing compiler which responds to these conflicting demands. The central idea of the approach is that the control during each cycle for each portion of the processor is explicitly represented in each instruction. Thus the pipelining is in effect statically determined by the compiler. The benefits of this approach include simpler hardware, avoiding unnecessary computations and that it allows the compiler to perform optimizations that are not possible on traditional architectures.