There and Back Again… a Datum's Tale

This work's focus is on the behavior analysis of data in the caching hierarchy. Especially as it pertains to the L1 data cache. Modern caching research often neglects detailed analysis of the current behavior found within the data cache and instead simply postulates as to the cause of degraded performance while suggesting a solution. Often it seems that such suggested work emerges from an idea, which upon success (improved performance or reduced power consumption), leads to a postulate detailing the reason for the improvement. This work will begin by modeling, as closely as possible, modern high performance processors: Intel Core i7-980x Extreme Edition and AMD Phenom II X6 Black 1090T. Such models will be executed via the M5 simulation environment on 32 benchmarks from Mediabench and the SPEC CPU2006 benchmark suites. Using these benchmarks, analysis of access patterns and thread behavior will be presented along with related work. Using unbiased analysis, this work will then present a possible caching configuration (SPLICE). SPLICE will then be tested using M5 in both single and multi-threaded environments. Additional analysis will provide a clear picture of how performance of a new configuration may be compared to its baseline in both single and multi-threaded environments. Most importantly, performance metrics will be presented in their respective chapters as each analysis is introduced. This work will conclude by re-affirming the need for deeper analysis when dealing with complex memory systems such as caches.