Performance Modeling and Analysis of a Centralized Fault Location and Identification System

The increasing interest and gradual adaptation of a DC electrical distribution system by the US navy and smart grid designs has demanded a change to the structure of the traditional electrical distribution system. The development of the power electronics has led to faster-operating devices and the goal to achieve fault clearance in ~8 ms requires a need for an ultra-fast fault location and identification system. The traditional protection system used in AC power distribution is well-understood and applied over a radial distribution system but may lack sufficient response times for a constantly adapting, intelligent, looped distribution structure. To assess the performance of the CFL system and to estimate the scaling of the CFL architecture, mathematical models are developed and are justified by supplementing with the actual testing results. This thesis presents a controller-hardware-in-the-loop (CHIL) testbed, interfacing RTDS with an industrial automation hardware, to demonstrate the methodology and to perform a comprehensive testing and analysis of a prototype of CFL system. The CFL system is based on ultrafast data communications and processing of sensor data to identify and determine the location of a fault in the medium voltage direct current (MVDC) shipboard power system (SPS). The results of CHIL experiments demonstrate ultrafast fault detection and precise fault location operation of the CFL system on a fault current limited MVDC SPS for a line-to-line fault under different operating conditions of the SPS. Mathematical models describing the relationship like the frame size, decision time and the operating time of the CFL system were developed and verified with the results obtained from an implemented CFL system. Factors affecting the performance and scaling for a practical CFL implementations were identified and analyzed. The models and analysis in this thesis are supported by experimental validation.