Power-Signal Integrated Gate Driver Design and Protection for Medium-Voltage SiC MOSFETs

The newly emerged medium-voltage (MV) silicon carbide (SiC) MOSFETs, spanning 2.5 kV to 15 kV range, are under the rapid developments and have received increasing attention recently. Compared to Si devices, SiC MOSFETs have significant improvements on the blocking voltage, specific on-resistance, switching speed and operating temperature. Therefore, MV SiC MOSFETs have a great potential to improve the efficiency and power density of MV converters, and meanwhile to drive down the system complexity. As the interface between MV SiC MOSFETs and control circuits, gate driver (GD) performance is critical to fully leverage the potential benefits of SiC devices as well as to enhance the reliability, such as the sufficient common-mode (CM) transient immunity (CMTI) and fast fault protection. Since there is little commercial GDs for MV SiC MOFETs, the research on MV GDs is still being explored, mainly focusing on the isolated GD power supply (GDPS) and fault protection designs. Existing MV GD solutions exhibit bulky size and high cost, since they not only require bulky GDPS to transmit GD power, but also need costly fiber optics (FOs) to transmit gate/ fault signals. State-of-the-art (SOA) GDPSs have demonstrated a reduced size aiming at the MV insulation requirement, but the total GD volume is still comparable or larger than the MV SiC devices. This dissertation proposes the power-signal integrated GD for MV SiC MOSFETs to minimize the GD footprint, which helps to integrate the GD into MV SiC device packages. This concept is utilized to firstly propose a 20-MHz dual-transformer-based isolated GD with power-signal integrated transmission. It not only removes costly FOs and bulky GDPSs, but also achieves the good timing performance including the full PWM duty-cycle range operation, low propagation delay time, and high PWM duty-cycle resolution. The solid-dielectrics-based insulation scheme is applied for proposed GD, which enables an insulating voltage > 10 kV rms for MV requirements as well as a moderate coupling capacitance to enhance the CMTI. The experimental results have verified the validity of proposed 20-MHz dual-transformer-based power-signal integrated GD for 3.3-kV and 10-kV SiC MOSFETs. To further reduce both the coupling capacitance and footprint of the power-signal integrated GD for MV SiC MOSFETs, a 50-MHz single-transformer-based design is then proposed, and its performance has been experimentally verified by driving 10-kV SiC MOSFET. The PD performance of GD transformer under the high frequency, high dv/dt PWM voltage excitation is also characterized using photo-multiplier tube method. Due to the lack of comprehensive and quantitative design principles, the conventional DESAT protection circuit parameters usually require trail-and-error efforts to achieve both the sufficient noise immunity to high dv/dt and fast fault response time. To address this issue, the quantitative design constraints and optimization methodology for DESAT circuit parameters are developed with little tuning work. The proposed DESAT circuit parameter design and optimization methodology has been experimentally verified on 3.3-kV SiC MOSFET module. The conventional DESAT protection scheme cannot be applied into switched-capacitor-based converters due to the inrush current spike occurring at the converter commutation. To eliminate the false-triggering issue induced by the inrush current, a novel charge-based DESAT protection scheme is proposed, where the "fault charge" rather than "fault current" is selected for the fault diagnosis. The proposed charge-based DESAT protection scheme considers the accumulation of fault current over time and thus can screen the narrow inrush current spikes with high magnitude. The proposed charge-based DESAT protection scheme has been designed and experimentally verified on 3.3-kV discrete SiC MOSFETs.